1-on-1 Online Training with Live Instructor
Focus on the fundamentals, solve problems, and work on real projects.
Portfolio and skill oriented outcomes. No credentials granted.
Learn while coding live with 1-on-1 help.
Hourly Learning Tracks
- 1-on-1 online with live instructor.
- Pay per hour. No commitment.
- No cohorts. Start immediately.
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Web Development Track
Learn coding and web development as you develop a portfolio of progressively larger projects.
Software Engineering Track
Focus on software architecture and practical team-oriented skills while developing knowledge of data structures and algorithms.
Chip Design Track
Study semiconductor design and verification using open source tools and PDKs.
Embedded Systems Track
Prepare for the future of embedded and operating system development by learning RISC-V and hardware-software co-design.
In-Depth Courses
- 1-on-1 online with live instructor.
- 24x 1-hour classes
- 2 hours of class per week over 3 months
- In-depth on a particular subject
- View the full course list.
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Pricing
Advanced Tracks
Software Engineering, Chip Design, or Embedded Systems
$100 / hour
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Register for Online Training
Cancellation Policy: Cancel anytime and don't pay for additional classes.
Billing: Monthly invoice.
Web Development Courses
Coding (Javascript or Python)
- Hello World / Fizz Buzz
- Math
- Conditionals / Logic / Booleans
- Strings
- Functions
- Loops
- Arrays
- Objects
-
Game Project
Start with a quick, free online tutorial.
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Web Development (Javascript/HTML/CSS)
- HTML basics
- CSS basics
- Javascript Browser Environment
- Sending GET Requests
- Setting up domain, DNS, SSL, nginx, and node
- Javascript Server Environment
- Handling GET Requests
- Sending POST Requests
- Handling POST Requests
- Database write
- Database read
-
Website Project
Start with a quick, free online tutorial.
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Intermediate Javascript (Javascript)
- Async Functions / Promises
- Event System
- DOM
- Object Methods
- Array Methods
- String Methods
- Regular Expressions
- Web APIs
-
Web App Frontend Project
Check out the course content and an example outline of the first few hours.
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Backend Engineering (Javascript/SQL)
- Nginx
- Node.js
- SQL
- NoSQL
- CAP Theorem
- ACID vs BASE
- REST API Design
- WebSockets
-
Web App Backend Project
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Software Engineering Courses
Software Architecture (multiple languages)
- Programming Paradigms
- Test Driven Development
- SOLID Principles
- 12 Factor App
- Continuous Integration / Agile
- Using Frameworks
- Evaluating Technologies
- Organizational Behavior
-
Software System Design Project
Textbook: Clean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
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Practical Software Engineering Techniques (multiple languages)
- Git
- Style Guides
- Debugging
- Refactoring
- Documentation
- Testing
- Pairing
- Zen of Python
- Convention vs. Configuration
- Principle of Least Astonishment
-
Open Source Contribution Project
Textbook: Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
Textbook: The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
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Machine Learning (Python/TensorFlow)
- Python Refresher (optional)
- TensorFlow Basics
- Layers
- Parameters
- Training
- Inference
- Models
- Transfer Learning
- Machine Vision
- Natural Language Processing
- Tensors
- ML Hardware
-
Image Classifier Project
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Computer Science (Python/C/Javascript)
- Graphs
- Trees
- Hash Tables
- Big O Notation
- Computational Complexity Classes
- Sorting
- Search
- Intro to Set, Order, and Category Theory
- Chomsky Hierarchy
-
Web Scale Project
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Systems Programming (C)
- Hello World / Fizz Buzz
- Math
- Conditionals / Logic / Booleans
- Strings
- Functions
- Loops
- Arrays
- Structs
- Pointers
- Defines
- Enums
- Compiler Flags
- ELF / ABI / Calling Conventions
-
Arduino Project
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Chip Design Courses
Digital Design (Verilog)
- Combinatorial Logic
- Intro to Verification
- Flip-Flops / Clock / Reset
- Gate Level Verilog
- Muxes / Buses
- Finite State Machines
-
Calculator Project
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Open Source VLSI (Verilog)
- Overview of Fabrication
- Overview of Design Process
- OSS Tools
- Writing Synthesizable Verilog
- Functional Verification
- Formal Verification
- Physical Domain Basics
- Power, Reset, and Clock
- Static Timing Analysis
- PSPICE
- Timing Corners
- PPA Optimization
-
SoC Module Project
Textbook: CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition),
Weste, Neil; Harris, David
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- Intro to Formal Property Verification (FPV)
- Assert, Cover, and Assume Statements
- Concurrent Assertions
- Properties and Sequences
- SMT Solvers
- TLA+
- Liveness
- Formal Equivalence Verification (FEV)
- Post-Silicon Debug
-
Cache Project
Textbook: Formal Verification: An Essential Toolkit for Modern VLSI Design,
Erik Seligman, et al.
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Computer Architecture (Verilog)
- Turing Machine / Von Neumann Architecture
- Accumulator Machines
- 6502 / 6800
- Classic RISC Pipeline
- DSP / VLIW
- Branch Prediction
- Superscalar
- SIMD
- Low-Power 2/3 stage pipelines
-
RISC-V Project
Textbook: Computer Architecture: A Quantitative Approach, Hennessy, John; Patterson, David
Textbook: The RISC-V Reader: An Open Architecture Atlas, Patterson, David; Waterman, Andrew
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STEM Essentials for EE
- Solving linear equations
- Higher order functions
- Kinematics
- Thermodynamics
- Information Theory
- Electromagnetics
- Electrochemistry
- Materials
- Statistics
- Scientific Method
-
System Design Project
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EE Core
- Circuit Theory
- Electronics
- RF
- Semiconductor Devices
-
Amplifier Project
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Analog / Mixed-Signal Design (Magic/Tcl/PSPICE)
- Magic
- PSPICE
- Transistor Model
- Opamp Design
- Design Iteration
- Parasitic Extraction
- Mixed-Signal Design
- PLL Design
-
ADC Project
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RF Design (Magic/Tcl/PSPICE)
- Super Heterodyne Transceiver
- Power Amplifier Design
- Low Noise Amplifier Design
- RF Mixer
- Impedence Matching
- Oscillators
- Inductors
- SERDES
-
915 Mhz Transceiver Project
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Low Power Design (PSPICE/Verilog/Python)
- Clock Gating
- Clock Domain Crossings
- Sychronizers
- Async FIFOs
- Frequency Scaling
- Microarchitecture for Low Power
- System Architecture for Low Power
-
Low Power ASIC Project
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SoC Design (PSPICE/Verilog/Python)
- RISC-V System Model
- Memory Map Design
- Bus Design
- Cache Hierarchy Design
- I/O Design
- Floorplanning
- Clock Domain Design
- Multiprocessor Systems
- Network-on-Chip
-
SoC Project
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Semiconductor Tech Seminar: Overview of Post-Denard Scaling Era Technologies
- FinFET
- FDSOI
- Advanced Packaging
- Wafer Processing
- UCI
- RFSOI
- SiC/GaN
- Aging
- Multiphysics Simulation
- EUV
- Post-FinFET
Primary Resource: semiengineering.com
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Embedded Systems Courses
PCB Design (KiCad)
- KiCad Basics
- BOM Costs
- Packages
- Schematics
- Wiring
- EMC
- Stackups
- Mixed-Signal
- Impedance Control
- Microstrip / Stripline
- Automation
- Board Level Simulation
- Assembly and Testing
- Enclosures and Product Packaging
- Certification Process
-
PCB Project
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Firmware Development (C/Zig)
- Bare Metal Environment
- Super Loop
- Task-based RTOS
- Device Drivers
- Boot
- Updates
- Constrained Device Patterns
- Cross Compilation
- Simulation
-
Firmware Project
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RISC-V Assembly Programming (RISC-V Assembly)
- RISC-V ISA
- Math
- Conditionals
- Loops
- Functions
- Traps
- Memory Map
- WebAssembly Intro
-
Platformer (Game) Project
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Hardware Security (C/TLA+/SVA)
- Hardware CWEs
- Networking
- Boot Vulnerablities
- Secure Update Patterns
-
OTA Update Project
Textbook: Security Engineering: A Guide to Building Dependable Distributed Systems, Anderson, Ross
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Compiler Design (Zig/Lox/C)
- Parsing
- Semantic Analysis
- Code Generation
- JIT Compilation
- Whole Program Analysis
-
Compiler Project
Textbook: Crafting Interpreters, Nystrom, Robert
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Operating System Design (Zig/Lox/C)
- Memory Management
- Process Management
- Scheduling
- Communication
- Linux
- FreeRTOS
-
Operating System Project
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Hardware-Software Co-Design (PSPICE/Verilog/Python + Zig/Lox/C + Javascript/HTML/CSS)
- Simulation Environments
- Scope of Simulation
- Build Systems
- FPGA-based Development
- Triple Stack (App + System SW + HW)
- Hardware Generation
- Automated Verification
- Triple Stack Proofs
- Performance Envelopes
- Economics of Co-Design
- Scraping / ETL / API + PDK Wrangling
- ML for Datasheets
-
IoT Project
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Special Course: Verilog for Software Engineers
Learn the basics of chip design and verification using Verilog.
At the end of the course you'll have a simulated design using the SKY130 open PDK.
Project: Create a custom I/O module and integrate it into a RISC-V SoC design using open source ASIC design tools
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About the Instructor
Steve Goldsmith is the founder and lead instructor of Aurifex Labs.
Steve worked for 6 years as a STEM tutor and Python coding teacher including co-founding Bay Area Summer Enrichment Camp where he taught Python to over 100 students.
Steve has developed games (Python/C++), audio software (C++), and web applications (JS/HTML/CSS).
He has also been researching compilers, computer architecture, programming languages, and VLSI.
Steve developed
Prospero
and is currently working on RISC-V design and verification.
Steve is passionate about teaching coding and has a BSEE.
Contact
Github
Open Source
Prospero
Source
Pair programming web app. Video, screen sharing, code editor, whiteboard, and file system.
Chiptastic
Source
Try
Open Source EDA tool; mostly a digital design place and route tool with a minimal set of standard gates, but you can draw all over it at various zoom levels. So it is really a high level design tool that can be used for floorplanning or bit-slice planning. The goal is to integrate with OpenLane, Skywater130 PDK, and other OSS EDA tools.
PSRAM Interface
Source
Reference RISC-V CPU (work in progress)
Source
External Resources
Canonical Online Resources
MDN
semiengineering.com
Textbooks
Clean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Weste, Neil; Harris, David
Formal Verification: An Essential Toolkit for Modern VLSI Design, Erik Seligman, et al.
Computer Architecture: A Quantitative Approach, Hennessy, John; Patterson, David
The RISC-V Reader: An Open Architecture Atlas, Patterson, David; Waterman, Andrew
Security Engineering: A Guide to Building Dependable Distributed Systems, Anderson, Ross
Crafting Interpreters, Nystrom, Robert
Skywater PDK
Skywater PDK - Open Source 130nm PDK
Consulting Services
Hourly VLSI / RISC-V Consulting
Services include: System Architecture, Microarchitecture, RTL Design,
Functional Verification, Timing Verification, Formal Verification, Physical Design, Board Design, and Hardware Security.
My ability to combine web development experience and VLSI/Comp Arch domain knowledge to quickly develop web-based EDA tools is a unique value offering.
$175 / hr
Quick Turnaround Web App Development
I will build a small web application (typically engineering oriented) designed for a single actual user (typically a technical SME).
See Chiptastic v0.1.
Delivery of a standalone web application of similar scope in 10 days.
It will be usable, i.e., not a prototype or proof-of-concept, but there will be bugs and workarounds. Data will most likely be stored as plain old JSON.
10 day deliverable: $10K
I can do a second iteration that fixes bugs and addresses workarounds that are in the user's path of flow. Delivered in 30 days.
Second iteration: $5K
Research Projects
These projects have been in development for years at this point and will be for years to come.
Aurifex Computer Family
The project that started and still drives Aurifex Labs. This has been in development for over a decade
and may well be in development another decade.
Workstation
A secure, collaborative desktop computer that let's you develop all the way down. Old school inspiration, but taking advantage of this new golden age of semiconductors.
Develop and debug datapaths like you would any other code without simulation and with real I/O.
Server
RISC-V deterministic, low-power cores for the cloud. 1U rack mount.
Can be custom built from standard log data on running production apps to
drastically
lower datacenter energy use or reduce latency.
Planned for the Aurifex Cloud.
Browser-on-a-chip
A low cost browser-on-a-chip based laptop for education and everyday use. All roads lead here; the prize at the bottom of the cereal box.
Dumb Phone
No app store. Security and privacy oriented. Low cost 5G dumb phone with text, voice, maps, and email.
Aurifex Cloud
Security: FIDO2 MFA + peer video ID proofing
Networking: Low latency with video conferencing and collaboration in mind
Compute: uServer - 25 MIPS RISC-V, 16 MB ram
Storage: Deterministic latency, hardware based security
Aurifex IoT Studio
RISC-V Consumer/Industrial/AgTech IoT Platform
Matter+5G capable RISC-V IoT platform with secure lifecycle (development, test, provisioning, ota updates, and decomissioning)
Targeting 130nm, 90nm, 65nm, 45nm, 28nm, and 22nm processes.
Culinary schools teach knife skills, not how to use infomercial products. Learn the tech equivalent of knife skills from a live instructor.
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