Textbook: Computer Architecture: A Quantitative Approach, John Hennessy; David Patterson
Textbook: The RISC-V Reader: An Open Architecture Atlas, David Patterson; Andrew Waterman
STEM Essentials for EE (Engineering Paper/Pencil)
- Solving linear equations
- Higher order functions
- Kinematics
- Thermodynamics
- Information Theory
- Electromagnetics
- Circuits
- Electrochemistry
- Materials
- Statistics
- Scientific Method
- System Design Project
Special Course: Verilog for Software Engineers
- Learn the basics of chip design and verification using Verilog
- 1-on-1 with hands-on project based learning
- At the end of the course you'll have a tested design that is ready to tapeout on Skywater 130nm process
- Project: Create a custom I/O module and integrate it into a RISC-V SoC design using open source ASIC design tools
Register for an Online Course
1-on-1 Courses with Live Instructor: $250 through September 1, 2022
Individual Rate; see pricing below for corporate / organization rates
About the Instructor
Steve Goldsmith is the founder and lead instructor of Aurifex Labs.
He worked for a number of years as a STEM tutor and Python coding teacher including co-founding Bay Area Summer Enrichment Camp where he taught Python to over 100 students.
He also has developed games (Python/C++), audio software(C++), and web applications(JS/HTML/CSS).
Steve has been studying compilers, computer architecture, programming languages, and VSLI for the past decade in pursuit of next generation general purpose computing.
He developed Prospero and is currently working on RISC-V cpu design and verification.
Steve is passionate about teaching coding and electrical engineering. He has a BSEE from Wilkes University.
Steve is currently reading Crafting Interpreters by Robert Nystrom.
He lives in Denver, Colorado, USA.
Open Source EDA tool; mostly a digital design place and route tool with a minimal set of standard gates, but you can draw all over it at various zoom levels. So it is really a high level design tool that can be used for floorplanning or bit-slice planning. The goal is to integrate with OpenLane, Skywater130 PDK, and other OSS EDA tools.
Services include: System Architecture, Microarchitecture, RTL Design,
Functional Verification, Timing Verification, Formal Verification, Physical Design, Board Design, and Hardware Security.
I am getting ready to tape out a 2-stage pipeline RISC-V design. I aim to be ready to provide comprehensive low-power SoC design and verification services by Q2 2023.
My ability to combine web development experience and VLSI domain knowledge to quickly develop web-based EDA tools is a unique value offering. I would love to engage with potential clients
as soon as possible to better understand the current needs of the rapidly changing semiconductor industry.
Embedded System / Linux Development (C/C++)
General Software Development (Python)
Full Stack Web Development (VanillaJS/NodeJS)
Debugging / Pairing (any language)
Need help debugging? I can help you get to the bottom of it; however deep the bottom is.
Quick Turnaround Web App Development
I will build a small web application (typically engineering oriented) designed for a single actual user (typically a technical SME).
See Chiptastic v0.1.
Delivery of a standalone web application of similar scope in 10 days.
It will be usable, i.e., not a prototype or proof-of-concept, but there will be bugs and workarounds. Data will most likely be stored as plain old JSON.
10 day deliverable: $15K
I can do a second iteration that fixes critical bugs and addresses workarounds that are in the user's path of flow. Delivered in 30 days.
Second iteration: $10K
Long Term Technology Platforms
These projects have been in development for years at this point and will be for years to come. Prices and business models are for design purposes; stong design, weakly held.
Aurifex Computer Family
The project that started and still drives Aurifex Labs. This has been in development for over a decade
and may well be in development another decade.
Server
RISC-V deterministic, low-power cores for the cloud. 1U rack mount.
Can be custom built from standard log data on currently running production apps to
drastically
lower datacenter energy use.
Planned for the Aurifex Cloud.
Workstation
A secure, collaborative desktop computer that let's you develop all the way down. Old school inspiration, but taking advantage of this new golden age of semiconductors.
Develop and debug datapaths like you would any other code without simulation and with real I/O.
Browser-on-a-chip
A low cost browser-on-a-chip based laptop for education and everyday use. All roads lead here; the prize at the bottom of the cereal box.
Dumb Phone
No app store. Security and privacy oriented. Low cost 5G dumb phone with text, voice, maps, and email.
Aurifex Cloud
Security: FIDO2 MFA + peer video ID proofing
Networking: Low-latency with video conferencing and collaboration in mind
Matter+5G capable RISC-V IoT platform with secure lifecycle (development, test, provisioning, ota updates, and decomissioning)
Targeting 130nm, 90nm, 65nm, 45nm, 28nm, and 22nm processes.
Obviously, these are big projects for a small company. The Golden Age of Semiconductors is upon us and we are are getting ready for the gold rush. Order your shovel now!
