Learn
coding
web dev
sw engineering
chip design
hw/sw co-design
1-on-1 online with live instructor
coding
web dev
sw engineering
chip design
hw/sw co-design
1-on-1 online with live instructor
In Development - Aurifex Open Cloud EDA running on DigitalOcean - Cloud based GDS viewer (maps-style) + MPW7 / Openlane image (tag 7a) + Admin tool powered by the DigitalOcean API
Coming 2023 (or so) - FDSOI course - Learn how to make ultra-low power, RF ASICs using open source tools on the first open FDSOI platform (SKY90-FD)
Focus on the fundamentals, solve problems, and work on real projects.
Portfolio and skill oriented outcomes. No credentials granted.
Learn using Prospero for video chat, screen sharing, and coding.
Interested in custom course content or a different format?
- 24x 2-hour 1-on-1 classes with flexible scheduling
- 4 hours of class per week over 3 months
- In-depth on a particular subject; semi-custom content based on individual goals
- 2x 1 hour 1-on-1 classes per week with flexible scheduling
- No cohorts. Start immediately. No commitment. Weekly billing.
- Only pay for weeks you schedule class.
Junior Web Developer Track
Learn coding and web development with progressively biggers projects designed to prepare you for an entry level web developer job.
Senior Software Engineer Track
Focus on software architecture and practical modern, team-oriented skills and learning new skills like ML.
Chip Designer Track
Study digital design and verification at your own pace using open source tools. Focus on learning core domain knowledge and guiding develop of the next generation of web-based EDA tools. Now with FDSOI! (We are going to start working on FDSOI specific tools even before the PDK is ready.)
Future of Embedded Systems Track
Prepare for the future of embedded and operating system development by learning RISC-V and hardware-software co-design. Work on developing open source reference IoT software for silicon that doesn't even exist yet.
First Week Free: Try Weekly Training for a week free with no commitment.
Cancellation Policy: Cancel anytime and don't pay for additional classes.
Start with a quick, free online tutorial.
Start with a quick, free online tutorial.
Check out the course content and an example outline of the first few hours.
Textbook: Clean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
Textbook: Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
Textbook: The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
Textbook: CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Weste, Neil; Harris, David
Textbook: Formal Verification: An Essential Toolkit for Modern VLSI Design, Erik Seligman, et al.
Textbook: Computer Architecture: A Quantitative Approach, Hennessy, John; Patterson, David
Textbook: The RISC-V Reader: An Open Architecture Atlas, Patterson, David; Waterman, Andrew
Primary Resource: semiengineering.com
Textbook: Security Engineering: A Guide to Building Dependable Distributed Systems, Anderson, Ross
Textbook: Crafting Interpreters, Nystrom, Robert
Learn the basics of chip design and verification using Verilog.
At the end of the course you'll have a tested design that is ready to tapeout on Skywater's 130nm process.
Project: Create a custom I/O module and integrate it into a RISC-V SoC design using open source ASIC design tools
Steve Goldsmith is the founder and lead instructor of Aurifex Labs.
Steve worked for 6 years as a STEM tutor and Python coding teacher including co-founding Bay Area Summer Enrichment Camp where he taught Python to over 100 students. Steve has developed games (Python/C++), audio software (C++), and web applications (JS/HTML/CSS).
For the past decade, he has been studying compilers, computer architecture, programming languages, and VLSI in pursuit of next generation general purpose computing. Steve developed Prospero and is currently working on RISC-V cpu design and verification.
Steve is passionate about teaching coding and electrical engineering, has a BSEE from Wilkes University, and lives in Denver, Colorado, USA.
Pair programming web app. Video, screen sharing, code editor, whiteboard, and file system.
Open Source EDA tool; mostly a digital design place and route tool with a minimal set of standard gates, but you can draw all over it at various zoom levels. So it is really a high level design tool that can be used for floorplanning or bit-slice planning. The goal is to integrate with OpenLane, Skywater130 PDK, and other OSS EDA tools.
PSRAM and PRNG
SourceRISC-V SoC
SourceClean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Weste, Neil; Harris, David
Formal Verification: An Essential Toolkit for Modern VLSI Design, Erik Seligman, et al.
Computer Architecture: A Quantitative Approach, Hennessy, John; Patterson, David
The RISC-V Reader: An Open Architecture Atlas, Patterson, David; Waterman, Andrew
Security Engineering: A Guide to Building Dependable Distributed Systems, Anderson, Ross
Crafting Interpreters, Nystrom, Robert
Matt Venn's Zero To Asic Course
Efabless Open MPW Shuttle Program
Skywater PDK - Open Source 130nm PDK
$375 / hr
Services include: System Architecture, Microarchitecture, RTL Design, Functional Verification, Timing Verification, Formal Verification, Physical Design, Board Design, and Hardware Security.
We are getting ready to tape out a 2-stage pipeline RISC-V design. We aim to be ready to provide comprehensive low-power SoC design and verification services by Q2 2023.My ability to combine web development experience and VLSI domain knowledge to quickly develop web-based EDA tools is a unique value offering. We would love to engage with potential clients as soon as possible to better understand the current needs of the rapidly changing semiconductor industry.
Need help debugging? We can help you get to the bottom of it; however deep the bottom is.
I will build a small web application (typically engineering oriented) designed for a single actual user (typically a technical SME).
See Chiptastic v0.1. Delivery of a standalone web application of similar scope in 10 days.
It will be usable, i.e., not a prototype or proof-of-concept, but there will be bugs and workarounds. Data will most likely be stored as plain old JSON.
10 day deliverable: $25K
I can do a second iteration that fixes critical bugs and addresses workarounds that are in the user's path of flow. Delivered in 30 days.
Second iteration: $15K
These projects have been in development for years at this point and will be for years to come. Prices and business models are for design purposes; stong design, weakly held.
The project that started and still drives Aurifex Labs. This has been in development for over a decade and may well be in development another decade.
RISC-V deterministic, low-power cores for the cloud. 1U rack mount. Can be custom built from standard log data on running production apps to drastically lower datacenter energy use or reduce latency. Planned for the Aurifex Cloud.
Security: FIDO2 MFA + peer video ID proofing
Networking: Low latency with video conferencing and collaboration in mind
Compute: uServer - 25 MIPS RISC-V, 16 MB ram
Storage: Deterministic latency, hardware based security
RISC-V Consumer/Industrial/AgTech IoT Platform
Matter+5G capable RISC-V IoT platform with secure lifecycle (development, test, provisioning, ota updates, and decomissioning)
Targeting 130nm, 90nm, 65nm, 45nm, 28nm, and 22nm processes.
A New Golden Age for Computer Architecture is upon us and it's time to get ready for the gold rush. Order your shovel now!
Culinary schools teach knife skills, not how to use infomercial products. Learn the tech equivalent of knife skills from a live instructor.