- 12x 1-hour sessions over 6-8 weeks with flexible scheduling
- Focus on the fundamentals
- Practice the basics and solve problems
- Work on a real project
- Culinary schools teach knife skills, not how to use infomercial products; I teach the tech equivalent of knife skills.
- Begin your journey to become a master of your craft or deepen your understanding of the skills you use everyday.
- Most of the time is spent on the final project for each course.
Learn using Prospero for video chat, screen sharing, coding, and running your code without installing anything
Start with a quick, free online tutorial.
Start with a quick, free online tutorial.
Check out a complete course outline.
Textbook: Clean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
Textbook: Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
Textbook: The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
Textbook: CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Weste, Neil; Harris, David
Textbook: Formal Verification: An Essential Toolkit for Modern VLSI Design, Erik Seligman, et al.
Textbook: Computer Architecture: A Quantitative Approach, John Hennessy; David Patterson
Textbook: The RISC-V Reader: An Open Architecture Atlas, David Patterson; Andrew Waterman
- Learn the basics of chip design and verification using Verilog
- 1-on-1 with hands-on project based learning
- At the end of the course you'll have a tested design that is ready to tapeout on Skywater 130nm process
- Project: Create a custom I/O module and integrate it into a RISC-V SoC design using open source ASIC design tools
1-on-1 Courses with Live Instructor: $250 through September 1, 2022
Individual Rate; see pricing below for corporate / organization rates
Steve Goldsmith is the founder and lead instructor of Aurifex Labs. He worked for a number of years as a STEM tutor and Python coding teacher including co-founding Bay Area Summer Enrichment Camp where he taught Python to over 100 students. He also has developed games (Python/C++), audio software(C++), and web applications(JS/HTML/CSS).
Steve has been studying compilers, computer architecture, programming languages, and VSLI for the past decade in pursuit of next generation general purpose computing. He developed Prospero and is currently working on RISC-V cpu design and verification.
Steve is passionate about teaching coding and electrical engineering. He has a BSEE from Wilkes University. Steve is currently reading Crafting Interpreters by Robert Nystrom. He lives in Denver, Colorado, USA.
- Foundational tech reskilling
- Project and skill based; No credentials granted
Read more about the current courses.
$450 / course $250 / course through September 1, 2022
Semiconductor Design Courses:
$750 / course $250 / course through September 1, 2022
Software Courses: $1000 / course
Semiconductor Design Courses: $1500 / course
Our on-site training programs will start after the pandemic ends.
Available now as an online class - 33% off of the on-site price
8 full day sessions over up to 3 weeks
Up to 12 participants
On-site Online class format
$20k as online class
12 full day sessions over up to 5 weeks
Up to 6 participants.
On-site Online class format
$30k as online class
Pair programming web app. Video, screen sharing, code editor, whiteboard, and file system.
Open Source EDA tool; mostly a digital design place and route tool with a minimal set of standard gates, but you can draw all over it at various zoom levels. So it is really a high level design tool that can be used for floorplanning or bit-slice planning. The goal is to integrate with OpenLane, Skywater130 PDK, and other OSS EDA tools.
PSRAM and PRNGSource
Clean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Weste, Neil; Harris, David
Formal Verification: An Essential Toolkit for Modern VLSI Design, Erik Seligman, et al.
Computer Architecture: A Quantitative Approach, Hennessy, John; Patterson, David
The RISC-V Reader: An Open Architecture Atlas, Patterson, David; Waterman, Andrew
Matt Venn's Zero To Asic Course
Efabless Open MPW Shuttle Program - MPW6 is due June 8, 2022
Skywater PDK - Open Source 130nm PDK
$175 / hr
Services include: System Architecture, Microarchitecture, RTL Design, Functional Verification, Timing Verification, Formal Verification, Physical Design, Board Design, and Hardware Security.I am getting ready to tape out a 2-stage pipeline RISC-V design. I aim to be ready to provide comprehensive low-power SoC design and verification services by Q2 2023.
My ability to combine web development experience and VLSI domain knowledge to quickly develop web-based EDA tools is a unique value offering. I would love to engage with potential clients as soon as possible to better understand the current needs of the rapidly changing semiconductor industry.
Need help debugging? I can help you get to the bottom of it; however deep the bottom is.
I will build a small web application (typically engineering oriented) designed for a single actual user (typically a technical SME).
See Chiptastic v0.1. Delivery of a standalone web application of similar scope in 10 days.
It will be usable, i.e., not a prototype or proof-of-concept, but there will be bugs and workarounds. Data will most likely be stored as plain old JSON.
10 day deliverable: $15K
I can do a second iteration that fixes critical bugs and addresses workarounds that are in the user's path of flow. Delivered in 30 days.
Second iteration: $10K
These projects have been in development for years at this point and will be for years to come. Prices and business models are for design purposes; stong design, weakly held.
The project that started and still drives Aurifex Labs. This has been in development for over a decade and may well be in development another decade.
RISC-V deterministic, low-power cores for the cloud. 1U rack mount. Can be custom built from standard log data on currently running production apps to drastically lower datacenter energy use. Planned for the Aurifex Cloud.
Security: FIDO2 MFA + peer video ID proofing
Networking: Low-latency with video conferencing and collaboration in mind
Compute: RISC-V environment
Storage: Fast, secure storage
RISC-V Consumer/Industrial/AgTech IoT Platform
Matter+5G capable RISC-V IoT platform with secure lifecycle (development, test, provisioning, ota updates, and decomissioning)
Targeting 130nm, 90nm, 65nm, 45nm, 28nm, and 22nm processes.
Obviously, these are big projects for a small company. The Golden Age of Semiconductors is upon us and we are are getting ready for the gold rush. Order your shovel now!