Open Silicon needs a Thorn in its Side
May 20, 2023
And I'll be it if I have to be.
Read the full post.
Direct link to this post: https://aurifexlabs.com/blog.html#may-24-2023
Opinionated ideas about HW/SW Co-Design, Semiconductor Design, and AI.
Open Silicon needs a Thorn in its Side
My Second Attempt at AI-assisted Hardware / Software Co-Design
Open Source Silicon: The Emperor Has No Clothes
Some Diagrams about HW/SW Co-Design
The Start of a Semiconductor Tool
Using Forth for Machine Bringup
My (Reductionist) View of Existential AI Risk and Regulation
May 20, 2023
And I'll be it if I have to be.
Read the full post.
Direct link to this post: https://aurifexlabs.com/blog.html#may-24-2023
May 20, 2023
I'll show rather than tell:
In order for this to be a reasonable approach I need a massive force multiplier. Based on these two attempts at code generation using phind, I feel pretty confident we are almost there. But I am still going to cling onto the late mover advantage a while longer.
A minimalist PC on STM32: https://www.phind.com/search?cache=a9b91825-2e69-474f-a2a0-bc6803a74331
Verilog from Simulator: https://www.phind.com/search?cache=1418c58b-ad15-46ee-94c5-c918bde63a56
Direct link to this post: https://aurifexlabs.com/blog.html#may-20c-2023
May 20, 2023
This paper is a great call to action, but I think it's missing something bigger. With papers like this one coming out seemingly every day, I think the era of generating machine code and silicon directly from LLMs is arriving sooner than I would have thought.
Direct link to this post: https://aurifexlabs.com/blog.html#may-20b-2023
May 20, 2023
If you are interested in open source silicon, I recommend reading this conversation I had with phind:
https://www.phind.com/search?cache=1418c58b-ad15-46ee-94c5-c918bde63a56
I'll let you draw your own conclusions, but for the time being I am going to steer clear of open silicon and focus on proper MPWs using commercial EDA tools and plan on using service providers like Muse, Europractice, and CMC.
Direct link to this post: https://aurifexlabs.com/blog.html#may-20-2023
May 9, 2023
When I launched the courses a year ago, this was the original syllabus; a learn all the things approach to HW/SW co-design.
In retrospect it seems a little ambitous...
Start with a quick, free online tutorial.
Start with a quick, free online tutorial.
Check out the course content and an example outline of the first few hours.
Textbook: Clean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
Textbook: Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
Textbook: The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
Textbook: CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Weste, Neil; Harris, David
Textbook: Formal Verification: An Essential Toolkit for Modern VLSI Design, Erik Seligman, et al.
Textbook: Computer Architecture: A Quantitative Approach, Hennessy, John; Patterson, David
Textbook: The RISC-V Reader: An Open Architecture Atlas, Patterson, David; Waterman, Andrew
Primary Resource: semiengineering.com
Textbook: Security Engineering: A Guide to Building Dependable Distributed Systems, Anderson, Ross
Textbook: Crafting Interpreters, Nystrom, Robert
Learn the basics of chip design and verification using Verilog.
At the end of the course you'll have a simulated design using the SKY130 open PDK.
Project: Create a custom I/O module and integrate it into a RISC-V SoC design using open source ASIC design tools
Direct link to this post: https://aurifexlabs.com/blog.html#may-9c-2023
May 9, 2023
A lot of the prose itself that went with these diagrams needs to be pulled from long email threads with various embedded system and semiconductor folks, but for now here are some random diagrams.
This is probably the most important diagram. My current take on co-design.
Here's where I think Aurifex Labs fits into the ecosystem. Everybody except Aurifex Labs are just examples.
One part of co-design I see emerging is "putting stakes in the ground" or more like pitons. Here's a HW piton for IoT:
I helped with the tapeout of a systolic array last fall. Here's the beating heart of a TPU:
Zooming in...
The CPU that this is the control unit for has been lost to the sands of time, but you can almost see the microarchitecture it if you look hard enough.
Direct link to this post: https://aurifexlabs.com/blog.html#may-9b-2023
May 9, 2023
After much consternation I have decided to simplify the course offerings and focus on AI.
Here are the major changes:
- Class size is now 3 instead of 5
- Courses have fixed start and end dates
- Stopped offering the Web Development progam and Intro to Python course
- Consolidated ML into a single course
These changes are based on an increased interest and personal focus on ML combined with learning from experience that splitting up the ML content into multiple courses didn't really make sense.
Direct link to this post: https://aurifexlabs.com/blog.html#may-9-2023
May 7, 2023
Take a look at Chiptastic
For now it doesn't do much, but you can do manual digital layout with some basic standard cells and draw on top of it.
The interface is pretty minimal so be sure to look at the status output in the bottom left corner of the screen and try out the hotkeys in the legend.
Beyond that just wire up some cells and draw using "Annotate".
And here's the source including an example of a halfway completed RISC-V cpu.
Direct link to this post: https://aurifexlabs.com/blog.html#may-7b-2023
May 7, 2023
Learning a new progamming language often changes the way we think about programming. Sometimes though a language will change the way you think about hardware too. Forth does both.
Forth is a stack based language, but I am going to focus on using it as a minimal language that can be implemented in a few days.
I created a Forth demo to see it running in the browser.
To understand Forth I would start by reading the jonesforth source (literate CISC at it's finest)
And here's the source for my little (incomplete) Forth including the emulator for the ad hoc assembly language.
Direct link to this post: https://aurifexlabs.com/blog.html#may-7-2023
April 15, 2023
I think there are some AI risks that are more immediate than others and things like bias and homogeneity are important, but I want to start with a simple mental model of a couple of broad classes of existential risk. I don't know if this is the right mental model, but it led to some interesting thoughts so here it is.
In the Emergent Takeover scenario, all actors in the universe may even be benevolent except a single artificial actor that simply due to it's size has emergent behaviors akin to survival instincts, but frequently emerge as an existential risk to humanity in an AI system of a certain size. This system is probably more heterogenous and complex (or complicated) than just an LLM. You could also call this the Skynet scenario.
In the Evil Attacker scenario, a human actor whose motivation is to do harm uses a superintelligence as a force multiplier. It could be a single high net worth individual whose mental health has been comprimised or a nation state using it as a nuclear-style deterrent even if designed to go unused, but what's in common is a purposeful and determined effort with significant resources to cause existential harm or the threat of existential harm. Think Bond villian.
I might have the ordering or spacing of the circles wrong. And there are interactions between risks that influence society in more subtle ways and these risks. At this point, I really have no idea, but it feels like it's something and at the same time feels like it's the result of a mind overfitted to movies.
Future posts will likely deal with more concrete aspects of ML. I wanted to start with the existential and drill down.
Direct link to this post: https://aurifexlabs.com/blog.html#apr-15-2023