Open Silicon needs a Thorn in its Side
May 20, 2023
by Steve Goldsmith
And I'll be it if I have to be.
Read the full post.
Direct link to this post: https://aurifexlabs.com/blog.html#may-24-2023
Aurifex Labs' Blog
Opinionated ideas about HW/SW Co-Design, Semiconductor Design, and AI.
2023
May
Open Silicon needs a Thorn in its Side
My Second Attempt at AI-assisted Hardware / Software Co-Design
Open Source Silicon: The Emperor Has No Clothes
Some Diagrams about HW/SW Co-Design
The Start of a Semiconductor Tool
Using Forth for Machine Bringup
April
My (Reductionist) View of Existential AI Risk and Regulation
My Second Attempt at AI-assisted Hardware / Software Co-Design
May 20, 2023
by Steve Goldsmith
I'll show rather than tell:
In order for this to be a reasonable approach I need a massive force multiplier. Based on these two attempts at code generation using phind, I feel pretty confident we are almost there. But I am still going to cling onto the late mover advantage a while longer.
A minimalist PC on STM32: https://www.phind.com/search?cache=a9b91825-2e69-474f-a2a0-bc6803a74331
Verilog from Simulator: https://www.phind.com/search?cache=1418c58b-ad15-46ee-94c5-c918bde63a56
Direct link to this post: https://aurifexlabs.com/blog.html#may-20c-2023
The LLM is the Compiler!
May 20, 2023
by Steve Goldsmith
This paper is a great call to action, but I think it's missing something bigger. With papers like this one coming out seemingly every day, I think the era of generating machine code and silicon directly from LLMs is arriving sooner than I would have thought.
Direct link to this post: https://aurifexlabs.com/blog.html#may-20b-2023
Open Source Silicon: The Emperor Has No Clothes
May 20, 2023
by Steve Goldsmith
If you are interested in open source silicon, I recommend reading this conversation I had with phind:
https://www.phind.com/search?cache=1418c58b-ad15-46ee-94c5-c918bde63a56
I'll let you draw your own conclusions, but for the time being I am going to steer clear of open silicon and focus on proper MPWs using commercial EDA tools and plan on using service providers like Muse, Europractice, and CMC.
Direct link to this post: https://aurifexlabs.com/blog.html#may-20-2023
The Original Curriculum
May 9, 2023
by Steve Goldsmith
When I launched the courses a year ago, this was the original syllabus; a learn all the things approach to HW/SW co-design.
In retrospect it seems a little ambitous...
Courses
- Coding
- Web Development
- Intermediate Javascript
- Backend Engineering
- Software Architecture
- Practical Software Engineering Techniques
- Machine Learning
- Computer Science
- Systems Programming
- Digital Design
- Open Source VLSI
- Formal Verification
- Computer Architecture
- STEM Essentials for EE
- EE Core
- Analog / Mixed-Signal Design
- RF Design
- Low Power Design
- SoC Design
- Semiconductor Tech Seminar
- PCB Design
- Firmware Development
- Assembly Programming
- Hardware Security
- Compiler Design
- Operating System Design
- Hardware-Software Co-Design
- Verilog for Software Engineers
Web Development Courses
Software Engineering Courses
Chip Design Courses
Embedded Systems Courses
Special Courses
Web Development Courses
Coding (Javascript or Python)
- Hello World / Fizz Buzz- Math
- Conditionals / Logic / Booleans
- Strings
- Functions
- Loops
- Arrays
- Objects
- Game Project
Start with a quick, free online tutorial.
Web Development (Javascript/HTML/CSS)
- HTML basics- CSS basics
- Javascript Browser Environment
- Sending GET Requests
- Setting up domain, DNS, SSL, nginx, and node
- Javascript Server Environment
- Handling GET Requests
- Sending POST Requests
- Handling POST Requests
- Database write
- Database read
- Website Project
Start with a quick, free online tutorial.
Intermediate Javascript (Javascript)
- Async Functions / Promises- Event System
- DOM
- Object Methods
- Array Methods
- String Methods
- Regular Expressions
- Web APIs
- Web App Frontend Project
Check out the course content and an example outline of the first few hours.
Backend Engineering (Javascript/SQL)
- Nginx- Node.js
- SQL
- NoSQL
- CAP Theorem
- ACID vs BASE
- REST API Design
- WebSockets
- Web App Backend Project
Software Engineering Courses
Software Architecture (multiple languages)
- Programming Paradigms- Test Driven Development
- SOLID Principles
- 12 Factor App
- Continuous Integration / Agile
- Using Frameworks
- Evaluating Technologies
- Organizational Behavior
- Software System Design Project
Textbook: Clean Architecture: A Craftsman's Guide to Software Structure and Design, Martin, Robert
Practical Software Engineering Techniques (multiple languages)
- Git- Style Guides
- Debugging
- Refactoring
- Documentation
- Testing
- Pairing
- Zen of Python
- Convention vs. Configuration
- Principle of Least Astonishment
- Open Source Contribution Project
Textbook: Code Complete: A Practical Handbook of Software Construction, McConnell, Steve
Textbook: The Pragmatic Programmer: Your Journey to Mastery, Thomas, David; Hunt, Andrew
Machine Learning (Python/TensorFlow)
- Python Refresher (optional)- TensorFlow Basics
- Layers
- Parameters
- Training
- Inference
- Models
- Transfer Learning
- Machine Vision
- Natural Language Processing
- Tensors
- ML Hardware
- Image Classifier Project
Computer Science (Python/C/Javascript)
- Graphs- Trees
- Hash Tables
- Big O Notation
- Computational Complexity Classes
- Sorting
- Search
- Intro to Set, Order, and Category Theory
- Chomsky Hierarchy
- Web Scale Project
Systems Programming (C)
- Hello World / Fizz Buzz- Math
- Conditionals / Logic / Booleans
- Strings
- Functions
- Loops
- Arrays
- Structs
- Pointers
- Defines
- Enums
- Compiler Flags
- ELF / ABI / Calling Conventions
- Arduino Project
Chip Design Courses
Digital Design (Verilog)
- Combinatorial Logic- Intro to Verification
- Flip-Flops / Clock / Reset
- Gate Level Verilog
- Muxes / Buses
- Finite State Machines
- Calculator Project
Open Source VLSI (Verilog)
- Overview of Fabrication- Overview of Design Process
- OSS Tools
- Writing Synthesizable Verilog
- Functional Verification
- Formal Verification
- Physical Domain Basics
- Power, Reset, and Clock
- Static Timing Analysis
- PSPICE
- Timing Corners
- PPA Optimization
- SoC Module Project
Textbook: CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Weste, Neil; Harris, David
Formal Verification (System Verilog Assertions)
- Intro to Formal Property Verification (FPV)- Assert, Cover, and Assume Statements
- Concurrent Assertions
- Properties and Sequences
- SMT Solvers
- TLA+
- Liveness
- Formal Equivalence Verification (FEV)
- Post-Silicon Debug
- Cache Project
Textbook: Formal Verification: An Essential Toolkit for Modern VLSI Design, Erik Seligman, et al.
Computer Architecture (Verilog)
- Turing Machine / Von Neumann Architecture- Accumulator Machines
- 6502 / 6800
- Classic RISC Pipeline
- DSP / VLIW
- Branch Prediction
- Superscalar
- SIMD
- Low-Power 2/3 stage pipelines
- RISC-V Project
Textbook: Computer Architecture: A Quantitative Approach, Hennessy, John; Patterson, David
Textbook: The RISC-V Reader: An Open Architecture Atlas, Patterson, David; Waterman, Andrew
STEM Essentials for EE
- Solving linear equations- Higher order functions
- Kinematics
- Thermodynamics
- Information Theory
- Electromagnetics
- Electrochemistry
- Materials
- Statistics
- Scientific Method
- System Design Project
EE Core
- Circuit Theory- Electronics
- RF
- Semiconductor Devices
- Amplifier Project
Analog / Mixed-Signal Design (Magic/Tcl/PSPICE)
- Magic- PSPICE
- Transistor Model
- Opamp Design
- Design Iteration
- Parasitic Extraction
- Mixed-Signal Design
- PLL Design
- ADC Project
RF Design (Magic/Tcl/PSPICE)
- Super Heterodyne Transceiver- Power Amplifier Design
- Low Noise Amplifier Design
- RF Mixer
- Impedence Matching
- Oscillators
- Inductors
- SERDES
- 915 Mhz Transceiver Project
Low Power Design (PSPICE/Verilog/Python)
- Clock Gating- Clock Domain Crossings
- Sychronizers
- Async FIFOs
- Frequency Scaling
- Microarchitecture for Low Power
- System Architecture for Low Power
- Low Power ASIC Project
SoC Design (PSPICE/Verilog/Python)
- RISC-V System Model- Memory Map Design
- Bus Design
- Cache Hierarchy Design
- I/O Design
- Floorplanning
- Clock Domain Design
- Multiprocessor Systems
- Network-on-Chip
- SoC Project
Semiconductor Tech Seminar: Overview of Post-Denard Scaling Era Technologies
- FinFET- FDSOI
- Advanced Packaging
- Wafer Processing
- UCI
- RFSOI
- SiC/GaN
- Aging
- Multiphysics Simulation
- EUV
- Post-FinFET
Primary Resource: semiengineering.com
Designing Chips Seminar: Tradeoffs in Alternatives to Traditional Compute
- Reconfigurable Hardware- Aynchronous Computers
- Analog Computation
- Quantum Computing
- Entropy and Gibb's Free Energy
Embedded Systems Courses
PCB Design (KiCad)
- KiCad Basics- BOM Costs
- Packages
- Schematics
- Wiring
- EMC
- Stackups
- Mixed-Signal
- Impedance Control
- Microstrip / Stripline
- Automation
- Board Level Simulation
- Assembly and Testing
- Enclosures and Product Packaging
- Certification Process
- PCB Project
Firmware Development (C/Zig)
- Bare Metal Environment- Super Loop
- Task-based RTOS
- Device Drivers
- Boot
- Updates
- Constrained Device Patterns
- Cross Compilation
- Simulation
- Firmware Project
RISC-V Assembly Programming (RISC-V Assembly)
- RISC-V ISA- Math
- Conditionals
- Loops
- Functions
- Traps
- Memory Map
- WebAssembly Intro
- Platformer (Game) Project
Hardware Security (C/TLA+/SVA)
- Hardware CWEs- Networking
- Boot Vulnerablities
- Secure Update Patterns
- OTA Update Project
Textbook: Security Engineering: A Guide to Building Dependable Distributed Systems, Anderson, Ross
Compiler Design (Zig/Lox/C)
- Parsing- Semantic Analysis
- Code Generation
- JIT Compilation
- Whole Program Analysis
- Compiler Project
Textbook: Crafting Interpreters, Nystrom, Robert
Operating System Design (Zig/Lox/C)
- Memory Management- Process Management
- Scheduling
- Communication
- Linux
- FreeRTOS
- Operating System Project
Hardware-Software Co-Design (PSPICE/Verilog/Python + Zig/Lox/C + Javascript/HTML/CSS)
- Simulation Environments- Scope of Simulation
- Build Systems
- FPGA-based Development
- Triple Stack (App + System SW + HW)
- Hardware Generation
- Automated Verification
- Triple Stack Proofs
- Performance Envelopes
- Economics of Co-Design
- Scraping / ETL / API + PDK Wrangling
- ML for Datasheets
- IoT Project
Special Course: Verilog for Software Engineers
Learn the basics of chip design and verification using Verilog.
At the end of the course you'll have a simulated design using the SKY130 open PDK.
Project: Create a custom I/O module and integrate it into a RISC-V SoC design using open source ASIC design tools
Direct link to this post: https://aurifexlabs.com/blog.html#may-9c-2023
Some Diagrams about HW/SW Co-Design
May 9, 2023
A lot of the prose itself that went with these diagrams needs to be pulled from long email threads with various embedded system and semiconductor folks, but for now here are some random diagrams.
This is probably the most important diagram. My current take on co-design.
Here's where I think Aurifex Labs fits into the ecosystem. Everybody except Aurifex Labs are just examples.
One part of co-design I see emerging is "putting stakes in the ground" or more like pitons. Here's a HW piton for IoT:
I helped with the tapeout of a systolic array last fall. Here's the beating heart of a TPU:
Zooming in...
The CPU that this is the control unit for has been lost to the sands of time, but you can almost see the microarchitecture it if you look hard enough.
Direct link to this post: https://aurifexlabs.com/blog.html#may-9b-2023
Re-organizing Courses
May 9, 2023
After much consternation I have decided to simplify the course offerings and focus on AI.
Here are the major changes:
- Class size is now 3 instead of 5
- Courses have fixed start and end dates
- Stopped offering the Web Development progam and Intro to Python course
- Consolidated ML into a single course
These changes are based on an increased interest and personal focus on ML combined with learning from experience that splitting up the ML content into multiple courses didn't really make sense.
Direct link to this post: https://aurifexlabs.com/blog.html#may-9-2023
The Start of a Semiconductor Tool
May 7, 2023
by Steve Goldsmith
Take a look at Chiptastic
For now it doesn't do much, but you can do manual digital layout with some basic standard cells and draw on top of it.
The interface is pretty minimal so be sure to look at the status output in the bottom left corner of the screen and try out the hotkeys in the legend.
Beyond that just wire up some cells and draw using "Annotate".
And here's the source including an example of a halfway completed RISC-V cpu.
Direct link to this post: https://aurifexlabs.com/blog.html#may-7b-2023
Using Forth for Machine Bringup
May 7, 2023
by Steve Goldsmith
Learning a new progamming language often changes the way we think about programming. Sometimes though a language will change the way you think about hardware too. Forth does both.
Forth is a stack based language, but I am going to focus on using it as a minimal language that can be implemented in a few days.
I created a Forth demo to see it running in the browser.
To understand Forth I would start by reading the jonesforth source (literate CISC at it's finest)
And here's the source for my little (incomplete) Forth including the emulator for the ad hoc assembly language.
Direct link to this post: https://aurifexlabs.com/blog.html#may-7-2023
My (Reductionist) View of Existential AI Risk and Regulation
April 15, 2023
by Steve Goldsmith
I think there are some AI risks that are more immediate than others and things like bias and homogeneity are important, but I want to start with a simple mental model of a couple of broad classes of existential risk. I don't know if this is the right mental model, but it led to some interesting thoughts so here it is.
In the Emergent Takeover scenario, all actors in the universe may even be benevolent except a single artificial actor that simply due to it's size has emergent behaviors akin to survival instincts, but frequently emerge as an existential risk to humanity in an AI system of a certain size. This system is probably more heterogenous and complex (or complicated) than just an LLM. You could also call this the Skynet scenario.
In the Evil Attacker scenario, a human actor whose motivation is to do harm uses a superintelligence as a force multiplier. It could be a single high net worth individual whose mental health has been comprimised or a nation state using it as a nuclear-style deterrent even if designed to go unused, but what's in common is a purposeful and determined effort with significant resources to cause existential harm or the threat of existential harm. Think Bond villian.
I might have the ordering or spacing of the circles wrong. And there are interactions between risks that influence society in more subtle ways and these risks. At this point, I really have no idea, but it feels like it's something and at the same time feels like it's the result of a mind overfitted to movies.
Future posts will likely deal with more concrete aspects of ML. I wanted to start with the existential and drill down.
Direct link to this post: https://aurifexlabs.com/blog.html#apr-15-2023